1. Field of the Invention
The present invention relates to semiconductor memory devices, and in particular, to Read-Only Memory (ROM) cell and the method for manufacturing the same.
2. Prior Art
Various elements, such as fuses, diodes, and transistors have been used on semiconductor substrate to implement the storage of bit contents of 0's and 1's for computing, communication, data processing, and information storage. A simple method is to have or not to have fuse or diode links between each address lines and data lines that determines the states of 0's and 1's. At the transistor level, more variations have been reported. For examples, enhancement type transistors and depletion type transistors are arranged on rows and columns to differentiate between 0's and 1's of the Read-Only memory cell contents, or ROM codes. The existence of contacts or not on the drain areas of the transistors is another way to do it. Furthermore, two types of transistors of low and high threshold voltages can be used also.
As the density of the bits per chip increases, ROM cells become smaller and smaller and structures become simpler. One cell that is compact and small is generally called "Flat Cell". FIG. 1a is a top plan layout view of a partial array arrangement represented by six such cells, C1 C2 . . . through C6. The cross sectional views taken along lines 1b--1b and 1c--1c of FIG. 1a are shown in FIG. 1b and FIG. 1c respectively. Such a cell includes a P-type Silicon substrate 10 having N+ diffusion bitlines 12 on the surface of the substrate 10 thereof. In between each adjacent N+ diffusion bitlines 12 are the channel regions 14. ROM codes are implemented by implanting some of the channel regions 14 of the transistors to a higher threshold voltages for storing 0's together with lower threshold transistors for storing 1's. Polysilicon wordlines 18 formed on an insulating film 16 over the channel regions 14 and N+ diffusion bitlines 12. P+ implanted regions 20 are used for cell isolation. The schematic diagram of the six cells shown in FIG. 1a is shown in FIG. 2. Such Flat Cell offer excellent packing density and simple in cell arrangement. However, such cell requires rather complicated controls of the peripheral circuitry, see for examples, Okada, et al., "16 Mb ROM Design Using Bank Select Architecture", Symposium on VLSI Circuits, Tokyo, Japan, Aug. 22-24 1988, Digest of Technical Papers, pp. 85-86, or T. Yiu, U.S. Pat. No. 5,117,389, issued May 26, 1992. Also, a very sensitive sense amplifier design is necessary to read the cell current and critical process control in order to match the design tolerance.